SOC
Nlview schematic (SVG)
clk
reset
data_mem
data_mem
clock
req[mem_req_load]
req[mem_req_store]
reset
resp[mem_ready]
req[mem_addr][57:0]
req[mem_data_out][511:0]
resp[mem_data][511:0]
core
core
clock
d_ready
d_valid
mem_bus_req[mem_req_load]
mem_bus_req[mem_req_store]
mem_bus_resp[mem_ready]
reset
d_addr[63:0]
d_rdata[63:0]
d_store_type[2:0]
d_wdata[63:0]
interrupt_sources[7:0]
mem_bus_req[mem_addr][57:0]
mem_bus_req[mem_data_out][511:0]
mem_bus_resp[mem_data][511:0]
RTL_REDUCTION_OR
RTL_REDUCTION_OR
O
I0[2:0]
RTL_AND__0
RTL_AND
I0
I1
O
RTL_AND__1
RTL_AND
I0
I1
O
timer
timer
MemRead
MemWrite
TimerAddress
TimerInterrupt
clock
enable
reset
address[63:0]
cycle[63:0]
data[63:0]
RTL_OR
RTL_OR
I0
I1
n/c
O
stdout
stdout
clock
enable
reset
stdout_taken
addr[63:0]
mem_store_type[2:0]
w_data[63:0]
RTL_OR__0
RTL_OR
I0
I1
O
RTL_AND
RTL_AND
I0
I1
O
VGA_clk
Hsync
VGA_b[3:0]
VGA_g[3:0]
VGA_r[3:0]
Vsync